The very first sentence: "Large language models (LLMs) have shown promise in register-transfer level (RTL) design automation" I want to see some serious proof for this shitty claim. While LLMs excel at slop webapp codegen because the code is usually highly modular, composable and easy to reason about), LLMs understanding of RTL is just pure dogshit. A simple signaling protocol, even well documented with some temporal behaviour and even some ready made assertions that are picked up by formal verification tools for static proving - none of this helps any top tier LLM to grok whats happening. state explosion, temporal dependencies, no composition - RTL is not code, its construction for complex machinery and LLM suck balls at it. and all of this will not go away if you slop into existence some low quality DSL for netlists
I've used AI successfully for some things but for SystemVerilog it's pretty rubbish. Too little training data I assume, and everything is behind firewalls.
However it's not completely useless - I've used it successfully for boilerplate for small demos and bug reproducers... And it has clarified some things for me (obviously I double checked what it said with the LRM). So I guess it's fair to say that they have "shown promise", in the same way that my 6 year old shows promise.
AI is advancing so quickly though, I bet it will be pretty good in a few years.
> RTL is not code
Of course it is. It executes on an unusual machine, but it's clearly code. I'll never understand this "hardware design is totally unlike software design" attitude that hardware designers have. Is it just so they feel special? They're really quite similar.
The very first sentence: "Large language models (LLMs) have shown promise in register-transfer level (RTL) design automation" I want to see some serious proof for this shitty claim. While LLMs excel at slop webapp codegen because the code is usually highly modular, composable and easy to reason about), LLMs understanding of RTL is just pure dogshit. A simple signaling protocol, even well documented with some temporal behaviour and even some ready made assertions that are picked up by formal verification tools for static proving - none of this helps any top tier LLM to grok whats happening. state explosion, temporal dependencies, no composition - RTL is not code, its construction for complex machinery and LLM suck balls at it. and all of this will not go away if you slop into existence some low quality DSL for netlists
I've used AI successfully for some things but for SystemVerilog it's pretty rubbish. Too little training data I assume, and everything is behind firewalls.
However it's not completely useless - I've used it successfully for boilerplate for small demos and bug reproducers... And it has clarified some things for me (obviously I double checked what it said with the LRM). So I guess it's fair to say that they have "shown promise", in the same way that my 6 year old shows promise.
AI is advancing so quickly though, I bet it will be pretty good in a few years.
> RTL is not code
Of course it is. It executes on an unusual machine, but it's clearly code. I'll never understand this "hardware design is totally unlike software design" attitude that hardware designers have. Is it just so they feel special? They're really quite similar.