Show HN: E80: an 8-bit CPU in structural VHDL

(github.com)

30 points | by Axonis 3 days ago ago

2 comments

  • bullen 14 hours ago ago

    16-bit address would have been good no? C64 > VIC2

    • Axonis 11 hours ago ago

      From a pedagogical aspect, probably yes. A 16 bit address bus would allow me to make a difference between a word and an address which would improve understanding of a real CPU. On the other hand, allowing the word and the address to be interchangeable makes assembly a bit easier.

      But the problem is that I'm using flip flops instead of a block RAM (see RAM.vhd, there's no PROCESS in it). As such I cannot take advantage of the internal FPGA ram. A 16bit address would be impossible to run on low cost FPGAs as it would require more than 500K flip flops.

      Finally, 255 bytes (+1 for the input) is good enough for the purpose of understanding and running textbook excersises to it, I think.