The question we all want the answer to is what is the current most likely contender for a decent performance widely available implementation of this profile, and when is it due?
I'm not aware of any chips, even in development, that will genuinely have full RVA23 support. If you'll settle for "near enough" then my betting is we'll have SiFive P650/P670 hardware first (https://www.sifive.com/cores/performance-p650-670). There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in very end 2025 / early 2026. These are server-class parts so the development boards will not be cheap.
Some parts of RVA23 like a complete implementation of the vector sub-extensions, and hypervisor support, are pretty complex.[1]
If you just want RVA23 now (with poor performance) then qemu implements it. We found it's not very useful for software development, not just because it's slow, but also because it performs so differently from the real hardware, so you cannot, for example, optimize your vectorized code.
> There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in 2026. These are server-class parts so the development boards will not be cheap.
I can get a 3A6000 system for 400€ with decent (~Zen2) performance, are we talking more than that?
But RISC-V predates loongarch64 - why did Loongson create a new ISA instead of implementing a fast RISC-V core?
Sure you can move faster if you can make your own standards and don't have to coordinate with anyone, but still makes me wonder if there is some fundamental issue that makes it difficult to create a high performance RISC-V implementation.
How does it compare to the current RISC-V leader, ESWIN SiFive P550?
Anyway, China seem to have decided to pursue a dual strategy of pouring money into RISC-V and LoongArch at the same time. I've no idea why that is. The company I work for talks to several RISC-V vendors who don't believe there is any issue with the RISC-V ISA for high performance server-class application cores.
The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008. In general, it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs and then addressed the bottlenecks over iterations.
> The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008.
Yes! And this is great progress in just a couple of years.
The previous SiFive core that made it to available hardware, the U74, is about like a Pentium or PowerPC 603 in µarch, though with higher clock speed so putting it more like late Pentium 3 or PowerPC G4 in delivered performance (and also quad core, not single core, which helps a lot).
SiFive already have 2 1/2 generations of core released since the P550 in mid 2021, the P670 and the P870(-D). Both of those implement RVV (Vector). If not for US sanctions we'd be seeing very nice 16x P670 machines this year, likely quite a bit better than the Pi 5 (and Rock 5 and Orange Pi 5). Or somewhere between Sandy Bridge and Skylake in Intel terms, I think.
The P870 is somewhere around Snapdragon 8 gen 2.
It just takes time to get CPU cores from the drawing board to shops, and especially for a company that wants to make consumer products to license the core in the first place since SiFive (like Arm) doesn't make chips.
RISC-V is behind Arm, but the gap in cores available to license is far smaller (about 2 years at present) than the gap in things anyone can buy in a shop (about 5 years at present) and getting smaller all the time.
> it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs
Because most of the market (by volume / revenue / profit) does not need the highest end CPUs.
Even in phones the Galaxy S25, with its Qualcomm Oryon cores, is a nice headline product, but there are still new SoCs and phones being introduced today (or at least there were some in February 2024 ... I haven't checked recently) with nothing faster than Arm A53 cores announced in 2012. I expect those low end phones are still selling in pretty big numbers.
Loongarch is built on MIPS, so the core predates RISC-V by decades.
RISC-V didn't have the specs to build what they were targeting when they started designing a few years ago. Given the similarities in the ISAs, I suspect they may switch to RISC-V in the near future.
It is a sad day in history to see both a RISC-V-related acronym and NDA used in the same sentence. The term oxymoron barely cuts it IMO. I thought that RISC-V used to stand for open hardware and freedom, TIL.
The RISC-V specs are all free to download and implement. Some (by no means all) implementations are proprietary. Red Hat (the company I work for) talks to all sorts of server vendors, x86, Arm, POWER, RISC-V all the time under NDA so we can find out what new products those vendors are developing before they are released, and have software ready in time. The software we write is all open sourced. This is nothing particular to do with RISC-V, and has nothing to do with the RISC-V ISA, nor with open sourcing of software.
My bets are on Tenstorrent Ascalon. They are currently taping out and planning to release a 8 core@2.25GHz devboard and laptop next year. The cores have an 8 wide decode/issue/dispatch and dual issue 256-bit RVV support.
Their the scalar part of their scheduling model is already upstream in LLVM as tt-ascalon-d8.
The only I can think of that may deliver earlier is Ventana with the Veyron V2, they plan to have chiplets in the first half of this year. I'm not sure if they are planning on releasing devboards though, as they target big servers. The cores have a 16 issue backend, with 5 512-bit RVV execution units (arithmetic,mask,permut,load,store) and a decode of up to 10 instructions per cycle.
Yes, they got access to a $2500 RISC-V machine that's been out for a year but isn't currently available because the same manufacturer has much updated machines coming out soon.
$2500 is more than a Raspberry Pi but not expensive for any organisation that is paying even one salary to one employee. I also note they recently got an Ampere Altra arm64 machine, which I believe start at around $4000.
Anyway, they blogged saying they were dropping RISC-V on March 12, got access to a RISC-V machine a couple of days later, mucked around a bit with build systems (including building a new Linux kernel that didn't advertise the pre-ratification V extension, which is a checkbox in `make menuconfig`) and then on March 20 -- 8 days after the initial post -- blogged that they had successfully completed a build of their distro on the donated RISC-V machine.
I don't know how long that complete build of all their packages took (Chimera Linux repo contains 11057 packages), but it can't have been more than 3 or 4 days, maybe less, which seems very reasonable.
I'm not sure what is "grim" here.
It's a very new ISA -- first ratified only in July 2019, and with very significant additions in November 2021 and more very important things (for RVA23, which will be the baseline for Android and also for Ubuntu 26.04 LTS) right up to 2024.
Machines are only going to get faster and cheaper from this point on, but a $2500 64 core 128 GB RAM machine from January 2024 that can build a complete distro in a couple of days isn't bad at all.
This release adds the cray style variable length vector instructions. Compiling with avx512 and running without it will crash, but this just uses whatever length the chip supports with the same instruction. Also means you don't have to wait on llvm to update every time they grow the vector size.
I don't get why they decided to create all these very complicated extensions before even getting solid hardware for the base instruction set. RVV support is many, many years into the future and I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway. Specifying standards for the future before you have working prototypes is very (ahaha) risky.
so completely the opposite complaint than https://news.ycombinator.com/item?id=43762141 which said RISC-V people should have skipped all the intermediate implementations and gone straight to x86-competitive competitive high performance cores.
i.e. they're probably doing something right.
When was the last successful and surviving today brand new ISA released that didn't offer backward compatibility with something that was already big in the market?
Not Aarch64 -- it coexisted with 32 bit Arm in all of Arm's cores from 2012 until 2023.
Not x86_64 which even to this days runs 32 bit (and 16 bit?) x86 code.
MIPS and SPARC are both gone, Alpha and Itanium were never huge and anyway are gone.
I guess IBM POWER, originally released as RS/6000 in 1990, 35 years ago. It had design lineage from 801/ROMP, but was not compatible with them.
There is solid hardware, it just not standard hardware for consumers. RVV support in software is already good and there are already many commercial chips.
> I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway
I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned.
What is more common is that people don't implement all the instructions in academic settings.
> Specifying standards for the future before you have working prototypes is very (ahaha) risky.
Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.
I looked at RISC-V SoCs last year and I couldn't find anything at all with support for RVV. Just a lot of "coming soon", "in progress", and "preorder now". Maybe the situation has improved since then.
The question we all want the answer to is what is the current most likely contender for a decent performance widely available implementation of this profile, and when is it due?
I'm not aware of any chips, even in development, that will genuinely have full RVA23 support. If you'll settle for "near enough" then my betting is we'll have SiFive P650/P670 hardware first (https://www.sifive.com/cores/performance-p650-670). There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in very end 2025 / early 2026. These are server-class parts so the development boards will not be cheap.
Some parts of RVA23 like a complete implementation of the vector sub-extensions, and hypervisor support, are pretty complex.[1]
If you just want RVA23 now (with poor performance) then qemu implements it. We found it's not very useful for software development, not just because it's slow, but also because it performs so differently from the real hardware, so you cannot, for example, optimize your vectorized code.
[1] I wrote a general article about RISC-V extensions last year: https://research.redhat.com/blog/article/risc-v-extensions-w...
> There are some other development boards coming (sorry, under NDA!) that should have near-RVA23 + Xeon-like performance and we should get them in 2026. These are server-class parts so the development boards will not be cheap.
I can get a 3A6000 system for 400€ with decent (~Zen2) performance, are we talking more than that?
[deleted - didn't realise you were talking about loongarch, see reply below]
But RISC-V predates loongarch64 - why did Loongson create a new ISA instead of implementing a fast RISC-V core?
Sure you can move faster if you can make your own standards and don't have to coordinate with anyone, but still makes me wonder if there is some fundamental issue that makes it difficult to create a high performance RISC-V implementation.
How does it compare to the current RISC-V leader, ESWIN SiFive P550?
Anyway, China seem to have decided to pursue a dual strategy of pouring money into RISC-V and LoongArch at the same time. I've no idea why that is. The company I work for talks to several RISC-V vendors who don't believe there is any issue with the RISC-V ISA for high performance server-class application cores.
> How does it compare to the current RISC-V leader, ESWIN SiFive P550?
I couldn't find many benchmarks of the P550, but at Phoronix it got beaten by a Raspberry Pi 4
https://www.phoronix.com/review/sifive-hifive-premier-p550
which the 3A6000 beats easiely
https://openbenchmarking.org/vs/Processor/Loongson-3A6000,AR...
The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008. In general, it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs and then addressed the bottlenecks over iterations.
> The P550 is pretty slow. It doesn't have any SIMD, and it's scalar engine is ~about the same as a Core 2 from ~2008.
Yes! And this is great progress in just a couple of years.
The previous SiFive core that made it to available hardware, the U74, is about like a Pentium or PowerPC 603 in µarch, though with higher clock speed so putting it more like late Pentium 3 or PowerPC G4 in delivered performance (and also quad core, not single core, which helps a lot).
SiFive already have 2 1/2 generations of core released since the P550 in mid 2021, the P670 and the P870(-D). Both of those implement RVV (Vector). If not for US sanctions we'd be seeing very nice 16x P670 machines this year, likely quite a bit better than the Pi 5 (and Rock 5 and Orange Pi 5). Or somewhere between Sandy Bridge and Skylake in Intel terms, I think.
The P870 is somewhere around Snapdragon 8 gen 2.
It just takes time to get CPU cores from the drawing board to shops, and especially for a company that wants to make consumer products to license the core in the first place since SiFive (like Arm) doesn't make chips.
RISC-V is behind Arm, but the gap in cores available to license is far smaller (about 2 years at present) than the gap in things anyone can buy in a shop (about 5 years at present) and getting smaller all the time.
> it's fairly confusing to me why SciFive has been so cautious in their designs. It seems like they would be in a much better place if they'd released a few CPUs where rather than trying to balance everything while creeping complexity up, they just added all the power to theoretically match high end CPUs
Because most of the market (by volume / revenue / profit) does not need the highest end CPUs.
Even in phones the Galaxy S25, with its Qualcomm Oryon cores, is a nice headline product, but there are still new SoCs and phones being introduced today (or at least there were some in February 2024 ... I haven't checked recently) with nothing faster than Arm A53 cores announced in 2012. I expect those low end phones are still selling in pretty big numbers.
> why did Loongson create a new ISA instead of implementing a fast RISC-V core?
Simple: They're a MIPS shop.
Loongarch is built on MIPS, so the core predates RISC-V by decades.
RISC-V didn't have the specs to build what they were targeting when they started designing a few years ago. Given the similarities in the ISAs, I suspect they may switch to RISC-V in the near future.
It is a sad day in history to see both a RISC-V-related acronym and NDA used in the same sentence. The term oxymoron barely cuts it IMO. I thought that RISC-V used to stand for open hardware and freedom, TIL.
The RISC-V specs are all free to download and implement. Some (by no means all) implementations are proprietary. Red Hat (the company I work for) talks to all sorts of server vendors, x86, Arm, POWER, RISC-V all the time under NDA so we can find out what new products those vendors are developing before they are released, and have software ready in time. The software we write is all open sourced. This is nothing particular to do with RISC-V, and has nothing to do with the RISC-V ISA, nor with open sourcing of software.
Riscv is an open ISA specification, not implementation
Organizations are free to make closed and even secret implementations of it if they like
That was not what the RISC-V supporters promised.
Who/where are those people, because they seem very misinformed
Most "RISC-V supporter" do at the very least understand what RISC-V is, and what it isn't.
I have never seen an actual RISC-V supporter confuse ISA and microarchitecture.
My bets are on Tenstorrent Ascalon. They are currently taping out and planning to release a 8 core@2.25GHz devboard and laptop next year. The cores have an 8 wide decode/issue/dispatch and dual issue 256-bit RVV support. Their the scalar part of their scheduling model is already upstream in LLVM as tt-ascalon-d8.
See also: https://youtu.be/ttQtC1dQqwo
The only I can think of that may deliver earlier is Ventana with the Veyron V2, they plan to have chiplets in the first half of this year. I'm not sure if they are planning on releasing devboards though, as they target big servers. The cores have a 16 issue backend, with 5 512-bit RVV execution units (arithmetic,mask,permut,load,store) and a decode of up to 10 instructions per cycle.
See also: https://youtu.be/OPgjCjNhqKQ
Both of these claim to support full RVA23 and are high perf OoO cores.
After Chimera Linux’s pessimistic view on RISC-V application processors, I’m not holding my breath
https://chimera-linux.org/news/2025/03/dropping-riscv.html
Note they eventually received a donation of CPU time that allows them to continue RISC-V support but it’s still a grim situation.
Yes, they got access to a $2500 RISC-V machine that's been out for a year but isn't currently available because the same manufacturer has much updated machines coming out soon.
$2500 is more than a Raspberry Pi but not expensive for any organisation that is paying even one salary to one employee. I also note they recently got an Ampere Altra arm64 machine, which I believe start at around $4000.
Anyway, they blogged saying they were dropping RISC-V on March 12, got access to a RISC-V machine a couple of days later, mucked around a bit with build systems (including building a new Linux kernel that didn't advertise the pre-ratification V extension, which is a checkbox in `make menuconfig`) and then on March 20 -- 8 days after the initial post -- blogged that they had successfully completed a build of their distro on the donated RISC-V machine.
I don't know how long that complete build of all their packages took (Chimera Linux repo contains 11057 packages), but it can't have been more than 3 or 4 days, maybe less, which seems very reasonable.
I'm not sure what is "grim" here.
It's a very new ISA -- first ratified only in July 2019, and with very significant additions in November 2021 and more very important things (for RVA23, which will be the baseline for Android and also for Ubuntu 26.04 LTS) right up to 2024.
Machines are only going to get faster and cheaper from this point on, but a $2500 64 core 128 GB RAM machine from January 2024 that can build a complete distro in a couple of days isn't bad at all.
This release adds the cray style variable length vector instructions. Compiling with avx512 and running without it will crash, but this just uses whatever length the chip supports with the same instruction. Also means you don't have to wait on llvm to update every time they grow the vector size.
The link is pretty light on details, should this be replaced with the 'read more' link within
Maybe link straight to the profile: https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/161547...
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I don't get why they decided to create all these very complicated extensions before even getting solid hardware for the base instruction set. RVV support is many, many years into the future and I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway. Specifying standards for the future before you have working prototypes is very (ahaha) risky.
so completely the opposite complaint than https://news.ycombinator.com/item?id=43762141 which said RISC-V people should have skipped all the intermediate implementations and gone straight to x86-competitive competitive high performance cores.
i.e. they're probably doing something right.
When was the last successful and surviving today brand new ISA released that didn't offer backward compatibility with something that was already big in the market?
Not Aarch64 -- it coexisted with 32 bit Arm in all of Arm's cores from 2012 until 2023.
Not x86_64 which even to this days runs 32 bit (and 16 bit?) x86 code.
MIPS and SPARC are both gone, Alpha and Itanium were never huge and anyway are gone.
I guess IBM POWER, originally released as RS/6000 in 1990, 35 years ago. It had design lineage from 801/ROMP, but was not compatible with them.
I can only speculate that the base was insufficient for high commercial traction.
There is solid hardware, it just not standard hardware for consumers. RVV support in software is already good and there are already many commercial chips.
> I bet many of its instructions will be micro coded since they aren't very useful for compilers anyway
I have listened to a lot of the talks about RISC-V and many about Vector extension, and micro-coding was barley mentioned.
What is more common is that people don't implement all the instructions in academic settings.
> Specifying standards for the future before you have working prototypes is very (ahaha) risky.
Absolutely nothing is standardized before hardware implementations exist. In fact, for Vector there was a first generation of the 0.7 that saw limited commercial use and far more more for the RVV 1.0 version.
I looked at RISC-V SoCs last year and I couldn't find anything at all with support for RVV. Just a lot of "coming soon", "in progress", and "preorder now". Maybe the situation has improved since then.